Charge-domain pipelined analog-to-digital converter

ABSTRACT

An ADC implementation of a bucket brigade type charge transfer pipeline using Metal Oxide Semiconductor (MOS) Bucket Brigade Devices (BBDs) that can be used in Analog-to-Digital (A/D) converters and other applications. In one embodiment a control circuit provides independent control of charge storage and charge transfer timing. Other arrangements provide high-speed and high-accuracy (A/D) conversion by employing a “boosted” charge-transfer circuit. The implementation can also achieve lower power consumption and improved resolution compared to other charge-domain methods by the use of a tapered pipeline, in which the amount of charge being processed is reduced in later pipeline stages compared to earlier ones. Still other embodiments enable implementing more than one decision threshold per stage, to support multi-bit resolution per stage and RSD-type A/D conversion algorithms.

INCORPORATED BY REFERENCE

This application claims the benefit of U.S. Provisional Application No. 60/901,597, filed on Feb. 15, 2007, U.S. Provisional Application No. 60/881,392, filed on Jan. 19, 2007, U.S. Provisional Application No. 60/881,967, filed on Jan. 23, 2007 and U.S. Provisional Application No. 60/900,675, filed on Feb. 9, 2007. The entire teachings of the above application(s) are incorporated herein by reference.

BACKGROUND OF THE INVENTION

In charge-domain signal-processing circuits, signals are represented as charge packets. These charge packets are stored, transferred from one storage location to another, and otherwise processed to carry out specific signal-processing functions. Charge packets are capable of representing analog quantities, with the charge-packet size in coulombs being proportional to the signal represented. Charge-domain operations such as charge-transfer are driven by ‘clock’ voltages, providing discrete-time processing. Thus, charge-domain circuits provide analog, discrete-time signal-processing capability. This capability is well-suited to performing analog-to-digital conversion using pipeline algorithms.

Charge-domain circuits are implemented as charge-coupled devices (CCDs), as MOS bucket-brigade devices (BBDs), and as bipolar BBDs. The present invention pertains to MOS BBDs.

Pipelined analog-to-digital converters (ADCs) are well-known in the general field of ADC design. They are widely used in applications in which high sample rates and high resolution must be combined. Pipelined ADCs implement the well-known successive-approximation analog-to-digital (A/D) conversion algorithm, in which progressively-refined estimates of an input signal are made at sequential times. In the pipelined version of this algorithm, one or several bits are resolved at each pipeline stage, the quantized estimate is subtracted from the signal, and the residue is propagated to the next pipeline stage for further processing. A commonly-used variation of the basic successive-approximation algorithm is the RSD algorithm, in which the resolution of each stage is finer than the stage's nominal bit-weight. This algorithm provides intrinsic digital code redundancy, which makes possible the relaxing of precision requirements on the comparators at each stage.

Pipelined ADCs have been implemented using a variety of circuit techniques, including switched-capacitor circuits and charge-domain circuits. The present invention pertains to charge-domain pipelined ADCs. All of the well-known algorithms used in conventional pipelined ADCs can be implemented using the circuit techniques of this invention

SUMMARY OF THE INVENTION

In the prior art, most pipelined ADCs have been implemented using switched-capacitor circuit techniques. In these circuits, signals are represented as voltages stored temporarily on capacitors. Signal pipelining is achieved through the use of MOS switches and op-amps. These methods consume relatively large amounts of power and are limited in sample-rate due to the requirement of using op-amps.

Charge-domain pipelined ADCs have the advantage of not requiring op-amps as essential components of the pipeline. Instead, they transfer charge packets directly from each pipeline stage to the next with essentially unity charge gain.

Prior-art charge-domain pipelined ADCs have been limited in accuracy or operating speed by various architectural deficiencies. BBD-based ADCs have suffered from non-linearity and other inaccuracies due to the imprecise nature of BBD charge transfer between pipeline stages. CCD-based implementations have suffered from excess power consumption due to the requirement of driving numerous CCD gates with high-speed clock signals.

The present invention provides an improved ADC implementation using MOS BBDs. This implementation achieves lower power consumption and improved resolution compared to other charge-domain methods by the use of a tapered pipeline, in which the amount of charge being processed is reduced in later pipeline stages compared to earlier ones. In one embodiment it provides high-speed and high-accuracy (A/D) conversion by employing an improvement on conventional BBDs known as a “boosted” charge-transfer circuit

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing will be apparent from the following more particular description of example embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating embodiments of the present invention.

FIG. 1 shows a simplified circuit diagram of a BBD charge-pipeline stage.

FIG. 2 illustrates voltage waveforms associated with FIG. 1.

FIG. 3 shows a two-stage BBD charge pipeline.

FIG. 4 illustrates voltage waveforms associated with FIG. 3.

FIG. 5 shows a BBD charge-pipeline stage including conditional charge addition.

FIG. 6 illustrates voltage waveforms associated with FIG. 5.

FIG. 7 shows a BBD charge-pipeline stage including conditional charge addition, with the added charge composed of two independent components.

FIG. 8 shows a single-ended BBD charge-pipeline stage including charge comparison.

FIG. 9 shows a differential BBD charge-pipeline stage including charge comparison.

FIG. 10 shows one stage of a differential charge-pipeline ADC which resolves one bit per stage.

FIG. 11 shows one stage of a differential charge-pipeline ADC which implements the RSD algorithm.

DETAILED DESCRIPTION OF THE INVENTION

A description of example embodiments of the invention follows. The teachings of all patents, published applications and references cited herein are incorporated by reference in their entirety.

MOS BBD pipelines are conventionally implemented using common-gate FETs as the charge-transfer devices, which convey charge from one pipeline stage to the next. In a previous patent application by the same inventor (U.S. patent application Ser. No. 11/807,914, filed May 30, 2007 entitled “Boosted Charge Transfer Circuit”) which is hereby incorporated by reference in its entirety, an improved class of charge-transfer circuits is disclosed and explained in detail. The ADC of the present invention can be implemented using either conventional or boosted charge-transfer circuits; the preferred embodiment employs the boosted charge-transfer circuit, which provides higher operating speed and accuracy. In the following discussion and figures charge-transfer circuits are represented abstractly and some behavioral aspects of these circuits are mentioned, but no details of the operation of such circuits are provided.

In the following description, all circuits are discussed assuming electrons as the signal-charge carriers and NFETs for signal-charge transfer. Identical circuits can be applied equally well using holes as charge carriers, by employing PFETs and reversed signal and control voltage polarities.

The basic principle of a BBD pipeline of the general type employed in this invention is described with the aid of FIG. 1, which depicts a single stage of such a pipeline. In this stage charge is stored on capacitor 5, which is connected between storage node 2 and voltage V_(C1). Charge enters the stage via charge-transfer circuit 1, and later exits the stage via charge-transfer circuit 3. Voltage V_(C1) is a digital clock signal which controls the timing of charge processing in the stage. Other digital clock signals, not shown, may be used to control the activity of the charge-transfer circuits.

Operating waveforms of the pipeline stage are shown in FIG. 2. At time t₀ clock voltage V_(C1) has a positive value 25. V₂, the voltage of storage-node 2 in FIG. 1, is also at a high initial voltage 21. At t₁ negative charge begins to be transferred from the previous stage (to the left of FIG. 1) via charge-transfer circuit 1 into the stage shown. As this negative charge accumulates on capacitor 5, V₂ falls to a more negative value. The voltage of node 2 settles to a relatively high value 22A if a relatively small negative charge was transferred; with a larger charge transferred, node 2 settles to a more negative voltage 22B. At time t₂ charge transfer into the stage is complete. The voltage of node 2 is related to the charge by the well-known expression Q=CV, where is the total capacitance of node 2. In FIG. 1, C is comprised of C₅, the capacitance of capacitor 5, plus any parasitic capacitance of node 2; such parasitic capacitance is usually small and is neglected in this discussion.

Charge transfer out of the stage begins at time t₃ when clock voltage V_(C1) switches to a low state. Capacitor 5 couples this voltage transition to node 2, driving V₂ low as well. Charge-transfer circuit 3 absorbs charge from capacitor 5, limiting the negative excursion of node 2, and eventually causing node 2 to settle to voltage 23 at t₄. Voltage 23 is a characteristic of charge-transfer circuit 3, and is independent of the amount of charge which had been stored on node 2. Charge-transfer circuit 3 transfers the charge absorbed from capacitor 5 to node 4 which is part of the stage following the one shown. After t₄ charge transfer is complete.

Finally, at time t₅, clock voltage V_(C1) returns to its initial state (voltage 25). Its positive-going transition is coupled to node 2 by capacitor 5, raising node 2 to voltage 24. Neglecting parasitic capacitance, no charge flows onto or off of node 2 during this transition; the voltage change of V₂ is therefore equal to the voltage change of V_(C1) during the transition at t₅. Since V₂'s value at the start of this transition, voltage 23, is independent of charge processed, voltage 24 is likewise independent of charge processed. This transition completes the operating cycle; the resulting voltage 24 at node 2 is thus the initial voltage for the next cycle. Thus the initial voltage state of the stage is constant cycle-to-cycle, and voltage 21=voltage 24. Consequently the initial and final charge on node 2 are also equal, and the charge transferred out is equal to the charge transferred in.

In summary: charge is transferred into the stage shown in FIG. 1 during t₁-t₂; between times t₂ and t₃ it is temporarily stored on capacitor 5, and is manifested as the value of V₂; during times t₃-t₄ this charge is completely transferred to the next stage; at t₅ the stage returns to its initial state, ready again to receive incoming charge. Thus the basic stage shown acts as a shift register for analog charge packets.

It should be understood that practical circuits depart in many details from this idealized description. Such departures include non-zero parasitic capacitance and imperfect charge transfer, for example. These effects, however, do not change the basic operating principles described above; and these principles can be applied in practical circuits with sufficient accuracy for useful purposes.

Conventional BBD charge pipelines have generally employed simple two-phase digital clock signals which simultaneously controlled the charge-storage capacitors and the charge-transfer FETs. Pipeline circuits such as that of FIG. 1 and others described below also operate using a two-phase clocking system. In these circuits, however, it is desirable to provide independent control of the activity of the charge-transfer circuits and of other clocked events in the stage such as capacitor switching. For this reason, the circuits of the present invention employ additional clock signals which control charge-transfer circuit activity. These signals and their function will be explained with the aid of FIGS. 3 and 4.

FIG. 3 shows a pipeline segment containing two successive stages, each like the basic pipeline stage of FIG. 1. This pipeline segment consists of first charge-transfer circuit 31, first storage node 32, and first capacitor 35, together constituting the first pipeline stage; second charge-transfer circuit 33, second storage node 34, and second capacitor 36, together constituting the second pipeline stage; and third charge-transfer circuit 37, which is the entry point of a next pipeline stage which is not shown. Clock voltages V_(C1) and V_(C2) drive the two capacitors respectively; and digital clock signals S_(CT1) and S_(CT2) control the charge-transfer circuits.

The waveforms associated with the operation of the circuit of FIG. 3 are shown in FIG. 4. The waveforms pertaining to the first stage in FIG. 3, V₃₂ and V_(C1), are identical with those of V₂ and V_(C1) respectively in FIG. 2. The waveforms pertaining to the second stage in FIG. 3, V₃₄ and V_(C2), are similar, but shifted by one-half of the clock cycle from those of the first stage. Thus the two stages of FIG. 3 operate on alternate half-cycles of the complete clock cycle. During the first half-cycle shown, when charge is transferring via charge-transfer circuit 31 into the first stage in FIG. 3, charge is transferring via charge-transfer circuit 37 out of the second stage (into the next stage, not shown). Likewise, during the second half-cycle, while charge is transferring out of the first stage via charge-transfer circuit 33, it is being transferred into the second stage.

In order to control the direction of charge transfer, it is necessary to selectively enable the appropriate charge-transfer circuits. The digital signals S_(CT1) and S_(CT2) provide this control. As shown in FIG. 4, S_(CT1) is asserted (high) during the interval t₁-t₂.This control signal enables charge-transfer circuits 31 and 37, which are active during this interval as described above. During the corresponding interval in the second half-cycle, t₃-t₄, S_(CT2) is asserted, enabling charge-transfer circuit 33. The exact means by which the digital signals S_(CT1) and S_(CT2) act to control the activity of the charge-transfer circuits is not pertinent to this invention. Some examples of such control are described in the aforementioned patent application (U.S. patent application Ser. No. 11/807,914, filed May 30, 2007 entitled “Boosted Charge Transfer Circuit”).

The two-phase operating mode just described is used in all of the pipeline circuits described below, together with control (by signals equivalent to S_(CT1) and S_(CT2)) of the charge-transfer circuits. In the interest of clarity, these details are not repeated in subsequent figures or descriptions.

In order to form a charge-domain ADC from a pipeline composed of stages similar to FIG. 1, a minimum of two operations in addition to charge storage and shifting are required: charges must be compared to a reference value, typically another charge; and a reference charge must be conditionally added to the signal charge (this ‘addition’ may be of either sign). In the ADC of this invention, these two operations are carried out in each of several pipeline stages. Implementation of these operations is explained below, beginning with the conditional addition of charge.

The basic principle employed for conditional charge addition is depicted in FIG. 5, with operating waveforms shown in FIG. 6. For the purposes of this discussion, a single-ended stage is shown. In practical ADC designs, differential operation is usually preferred; both modes are possible within the scope of this invention.

The pipeline stage shown in FIG. 5 retains all the elements shown in FIG. 1. In addition, FIG. 5 includes two new elements: capacitor 6 (with value C₆) connected between charge-storage node 2 and voltage V_(QR1); and switch 7 connected between node 2 and voltage V_(P). Switch 7 is controlled by a periodic digital clock signal (identified as S₇ in FIG. 6).

FIG. 6 shows the operating waveforms of the circuit of FIG. 5. The initial conditions in FIG. 6 are similar to those in FIG. 2: V_(C1) is at high voltage 45 and V₂, the voltage of node 2, is at high voltage 41. In addition, V_(QR1) is at high voltage 47, and switch 7 is in an off state, indicated by the low value of its control signal S₇ in FIG. 6. As in FIG. 2, charge is transferred into the stage between t₁ and t₂, causing V₂ to fall in proportion to the incoming charge, settling at voltage 42. The change in V₂ due to incoming charge is inversely proportional to the total capacitance of node 2 as explained above. In FIG. 5 (neglecting parasitic capacitance) this total capacitance is C=C₅+C₆.

After the charge is transferred in, the new features of FIG. 5 come into play. At time t_(3A) voltage V_(QR1) conditionally switches from its high state 47 to low state 48. This conditional transition of V_(QR1) is coupled via C₆ to node 2 where, because of capacitive division, it produces a similar but smaller voltage change. The voltage at node 2 changes to voltage 49 (dashed line) if V_(QR1) switches, and remains at voltage 42 (solid line) if it does not.

At time t₃, V_(C1) switches from high voltage 45 to low voltage 46, instigating charge transfer out of the stage. As explained with reference to FIG. 2, node 2 is driven to a lower voltage due to coupling via capacitor 5. Charge-transfer circuit 3 removes charge from node 2 and transfers it to the next stage. By t₄ V₂ settles to voltage 43 which is independent of the charge previously on node 2, and charge transfer out of the stage is complete.

At t₅ both V_(C1) and V_(QR1) return to their initial high states (voltages 45 and 47 respectively). This transition is identical for V_(C1) in every clock cycle. V_(QR1), however, may already be at its high voltage 47, depending on whether or not it switched at t_(3A). Thus the positive step coupled to node 2 at t₅ can have different values, depending on the state of V_(QR1), resulting in a different final voltage. The added switch 7 in FIG. 5 is used to restore the voltage (and charge) on node 2 to a repeatable state regardless of the state of V_(QR1) at t₅. Switch 7 is turned on, as indicated by the high state of its control signal S7, during t₅-t₆, thus establishing a repeatable voltage at node 2 to begin the next cycle, so voltage 44=voltage 41. With an ideal switch, voltage 44=V_(P); practical MOS switches introduce a small ‘pedestal’ so that voltage 44≠V_(P). This non-ideality is, however, repeatable cycle-to-cycle, so the voltage 44=voltage 41 condition is still met in practical circuits.

Unlike the case of FIG. 1 where the charge transferred into the stage was subsequently transferred out without alteration, the outgoing charge in the circuit of FIG. 5 differs in general from the incoming charge: Q _(OUT) =Q _(IN) +C ₆ ΔV _(QR1) +Q _(CONST)  Equation 1 where C₆ is the capacitance of capacitor 6, ΔV_(QR1) is the change in V_(QR1) at t_(3A), and Q_(CONST) is a fixed charge which depends on V_(P), voltages 43, 45, and 46, and the capacitor values. As is apparent in FIG. 6, ΔV_(QR1) is equal to (voltage 48-voltage 47) if V_(QR1) switches, and is equal to zero if it does not. Note that both C₆ΔV_(QR1) and Q_(CONST) can be either positive or negative quantities.

When the circuit of FIG. 5 is used to form one stage of a pipelined ADC, the quantity (voltage 48-voltage 47) is made equal to a reference voltage; for convenience it will be called V_(R1). Correspondingly, the quantity C₆V_(R1) becomes a reference charge, since C₆ is fixed in a given instantiation. Thus the conditional choice of ΔV_(QR1)=V_(R1) or ΔV_(QR1)=0 at t_(3A) corresponds in Equation 1 to the conditional addition of a reference charge C₆V_(R1) to the incoming charge packet Q_(IN). The circuit of FIG. 5 thus provides one of the two operations required for charge-domain ADC implementation.

Note that the exact position of time t_(3A) is not critical to the operation of the circuit of FIG. 5. The conditional transition of V_(QR1) can occur at any time between t₀ and t₃ with no change in circuit performance; under some practicable conditions it may also occur in the t₃-t₄ interval.

In some ADC implementations it is desirable to provide more than one conditional charge addition in a single pipeline stage. An example of such a stage is shown in FIG. 7. This circuit includes, in addition to the elements in FIG. 5, additional capacitor 6A and voltage source V_(QR2). The operation of such a stage is identical to that of FIG. 5, except that at t_(3A) each of the voltages V_(QR1) and V_(QR2) undergoes an independent conditional transition, of size V_(R1) or V_(R2) respectively. The resulting charge transfer function of the stage is given by: Q _(OUT) =Q _(IN) +C ₆ ΔV _(QR1) +C _(6A) ΔV _(QR2) +Q _(CONST)  Equation 2 The same principle can be extended to any number of capacitors and V_(R) values.

The remaining operation required for charge-domain ADC operation is charge comparison. FIG. 8 shows a circuit which provides this operation. The circuit of FIG. 8 is identical to that of FIG. 1, with the addition of voltage comparator 8 and latch 9.

Comparator 8 compares the voltage of node 2 with a reference voltage V_(RC). As was pointed out in connection with FIGS. 1 and 2, the voltage at node 2 after t₂ depends on the amount of charge transferred into the stage: in FIG. 2, for example, two different incoming charge quantities result in voltages 22A and 22B respectively at node 2. Because of this dependence, voltage comparator 8 accomplishes a compison of charge on node 2 vs. a reference. Latch 9 captures the result of this comparison at a time between t₂ and t₃ defined by the digital clock signal V_(C2), and provides a digital output voltage V_(B).

As was mentioned above, many practical charge-domain pipelined ADCs employ differential circuitry. In such circuitry, signals are represented by pairs of charges whose difference is proportional to the signal. This arrangement permits representation of bipolar signals with unipolar charge packets, and can also provide dynamic range and noise-immunity benefits.

FIG. 9 illustrates a differential pipeline stage which is functionally similar to the single-ended stage of FIG. 8. The circuit of FIG. 9 contains two charge pipelines, each identical to that of FIG. 1. The upper pipeline contains elements 1A, 2A, 3A, 4A and 5A, equivalent to elements 1, 2, 3, 4, and 5 in FIG. 1. The lower pipeline contains elements 1B . . . 5B, also equivalent to elements 1 . . . 5 of FIG. 1. The latch 9 in this circuit serves the same function as in FIG. 8. In this differential configuration, however, the comparator 8 compares the voltages of the two charge storage nodes 2A and 2B, rather than comparing to a fixed reference as in FIG. 8. Thus the comparator decision in FIG. 9 is based on the sign of the differential charge signal during the t₂-t₃ interval.

The several circuit configurations described above provide all the operations needed to carry out pipelined charge-domain A/D conversion: namely charge storage and transfer, charge comparison, and conditional and constant charge addition. These operations can be combined in various ways to carry out a variety of ADC algorithms. Two examples of ADCs based on these operations are given below: one which implements a basic one-bit conversion per pipeline stage; and one which implements an RSD (sometimes called “1.5 bit”) conversion per pipeline stage.

FIG. 10 illustrates a differential charge-domain pipeline ADC stage which resolves one bit per stage. The circuit shown combines the basic differential pipeline, comparator, and latch of FIG. 9 with the conditional charge-addition capability of FIG. 5 (used here in differential form). These elements are all identified similarly to the corresponding elements in the previous figures, and operate in the same manner. In addition the circuit of FIG. 10 includes a block of logic circuitry consisting of inverter 71 and OR-gates 72 and 73, plus level-shifters 74 and 75.

In operation, each of the two pipelines operates like the circuit of FIG. 5, with V_(QR1A) and V_(QR1B) each functioning for its respective pipeline like V_(QR1) in FIG. 5. The logic block in FIG. 10 causes either V_(QR1A) or V_(QR1B) (but not both) to switch from a high to a low state at the appropriate time. The exact high and low voltages, V_(H) and V_(L), are provided in response to the logic levels at the OR-gate outputs by the level shifters 74 and 75. Operating waveforms for each of the two pipelines in this circuit are the same as those in FIG. 6. Clock voltage V_(C3) determines the timing of V_(QR1A/B) switching, equivalent to t_(3A) in FIG. 6. Latch 9 is clocked (by clock voltage V_(C2)) at a time before or coincident with V_(QR1A/B) switching.

As a result of these operating conditions, the two pipelines in FIG. 10 process charge in accordance with the following equations: Q _(OUTA) =Q _(INA) +C ₆ ΔV _(QR1A) +Q _(CONST)  Equation 3A Q _(OUTB) =Q _(INB) +C ₆ ΔV _(QR1B) +Q _(CONST)  Equation 3B where C₆ is the value of capacitors 6A and 6B and ΔV_(QR1A) and ΔV_(QR1B) are equal either to ΔV_(R)=V_(L)−V_(H), or to zero. (It is assumed here for simplicity that the values of capacitors 6A and 6B are equal, and that both are driven by the same value of ΔV_(QR); neither of these constraints are essential.) The dependence of the conditional charges in equations 3A and 3B on the comparator decision can be expressed as: C ₆ ΔV _(QR1A) =bC ₆ ΔV _(R)  Equation 4A C ₆ ΔV _(QR1B)=(1−b)C ₆ ΔV _(R)  Equation 4B where b is the value of the output bit decision, with value 1 or 0.

In the differential pipeline configuration, the signal is represented by the difference between the “A” charge and the “B” charge: Q=Q_(A)−Q_(B). Thus Equations 3A, 3B, 4A and 4B may be combined to express the overall stage transfer function for differential signal charge: Q _(OUT) =Q _(IN)+(2b−1)C ₆ ΔV _(R) =Q _(IN)+(2b−1)Q _(STAGE)  Equation 5 where we have defined Q_(STAGE)=C₆ΔV_(R). Equation 5 shows that the stage either adds Q_(STAGE) to the incoming charge (if b=1) or subtracts Q_(STAGE) from the incoming charge (if b=0). This operation is recognizable as one step in the well-known successive-approximation algorithm for A/D conversion, as applied to a signed signal.

A pipeline of N such stages thus produces the charge transfer function: Q _(OUT(N)) =Q _(IN)+(2b ₁−1)Q _(STAGE(1))+(2b ₂−1)Q _(STAGE(2)) . . . +(2b _(N)−1)Q _(STAGE(N))  Equation 6

If each stage-charge Q_(STAGE(k+1)) is smaller than the preceding one, Q_(STAGE(k)), then this series of charge comparisons and (signed) additions converges towards Q_(OUT(N))=0. In particular, if the stage-charges are scaled such that Q_(STAGE(k+1))=(½)·Q_(STAGE(k)), then the sequence of comparator decisions b₁, b₂, . . . b_(N) constitute the bits of an N-bit offset-binary approximation to the ratio Q_(IN)/2Q_(STAGE(1)). In this case, the full-scale-range that can be approximated is −2Q_(STAGE(1))≦Q_(IN)<2Q_(STAGE(1)).

One property of this algorithm is that, for pipeline input signals that are within the full-scale range of the conversion process, the output differential charge from each stage (k) obeys the condition: |Q_(OUT(k))|≦|Q_(STAGE(k))|  Equation 7

Thus each successive stage needs to process less differential charge than the previous stage. For binary stage scaling, each successive stage needs to process at most half the charge of the previous stage. This fact makes possible another advantage of the present invention.

As was pointed out above, the voltage change at the charge storage node (node 2 in FIG. 5, for example) is ΔV=Q_(IN)/C, where C is the total capacitance at the node. In a practical charge-domain circuit, the maximum voltage change ΔV at the storage node must be constrained within limits dictated by the semiconductor process used, available clock voltages, etc. For a given charge entering the stage, such limits impose a minimum possible size on total node capacitance in the stage; if we call the maximum allowable voltage swing at the charge storage node ΔV_(MAX), then we can express the limit on node capacitance as: C _(NODE) >Q _(IN) /ΔV _(MAX)  Equation 8

A large C_(NODE) value, however, has a disadvantage: it reduces the voltage presented to the comparator by a given charge signal. Consequently for a given comparator voltage resolution (limited by voltage noise or offset, for example) the minimum resolvable charge is inversely proportional to C_(NODE). It would be desirable to reduce C_(NODE) as much as possible, in order to maximize charge resolution (and thus overall ADC resolution in effective bits). Thus the constraint in Equation 8 is in conflict with the goal of high ADC resolution.

The present invention provides a means of satisfying Equation 8 while providing high ADC resolution. Equation 7 indicates that the differential charge signal which each stage in a pipeline needs to process is reduced compared to the previous stage. (It is reduced by a factor of two in a binary pipeline.) Thus the minimum allowable node capacitance required to satisfy Equation 8 with respect to the differential signal charge is smaller for each successive pipeline stage. In order to exploit this opportunity, however, not only the differential charge, but the individual charges comprising the differential pair must be reduced at each successive stage.

The common-mode (CM) charge at each stage is defined as the average of these two charge packets. Even though the signal charge (i.e., the charge-packet difference) is reduced at each stage by the combined actions of comparator and charge addition, the CM charge is not. Using its definition, we can combine Equations 3A, 3B, 4A and 4B and the definition of Q_(STAGE) to obtain:

$\begin{matrix} \begin{matrix} {Q_{{CM} - {OUT}} = {{1/2}\left( {Q_{OUTA} + Q_{OUTB}} \right)}} \\ {= {{1/2}\begin{Bmatrix} {\left( {Q_{INA} + Q_{INB}} \right) +} \\ {{\left\lbrack {b + \left( {1 - b} \right)} \right\rbrack C_{6}\Delta\; V_{R}} + {2Q_{CONST}}} \end{Bmatrix}}} \\ {= {Q_{{CM} - {IN}} + {{1/2}C_{6}\Delta\; V_{R}} + Q_{CONST}}} \\ {= {Q_{{CM} - {IN}} + {{1/2}Q_{STAGE}} + Q_{CONST}}} \end{matrix} & {{Equation}\mspace{20mu} 9} \end{matrix}$

Equation 9 shows that the CM charge changes at each stage by a fixed amount characteristic of that stage. (This amount is independent of the stage's bit decision.) As discussed above, Q_(STAGE) depends on C₆ and ΔV_(R), while Q_(CONST) depends on C₅ and several other voltages. Thus it is possible to select values of C₆ and V_(P), for example, to cause Q_(CM-OUT) to decrease from stage to stage just as Q_(STAGE) does. The result is that the total capacitance of each stage can be made smaller than the previous one; for binary scaling, it can be approximately one-half the size.

The pipelined ADC architecture incorporating this charge and capacitance reduction from stage to stage is termed a “tapered pipeline”. It has several important advantages over prior-art BBD-based ADCs: by reducing total capacitance for a series of stages, it reduces operating power; for the same reason it reduces the total “kTC” noise added in the pipeline (thus improving ADC resolution); it increases the charge resolution of comparators in later stages of the pipeline, thus making possible higher overall resolution; and it reduces the total capacitance required for the pipeline, thus reducing circuit area.

In order to exploit the increased comparator charge resolution available in later pipeline stages in a tapered pipeline, an algorithm must be employed which prevents inexact comparator decisions in early stages from compromising precision of the final A/D conversion. A well-known solution to this requirement is the employment of redundancy, such that later stages are able to correct for inexact early decisions. A widely-used algorithm based on this concept is the RSD (sometimes referred to as the “1.5 bit-per-stage”) algorithm. In this approach, each pipeline stage has two independent comparators with differing thresholds, and two corresponding pairs of conditionally-switched capacitors. The RSD algorithm has been widely implemented in switched-capacitor pipelines, but not previously in charge-domain pipelines. Its use in a BBD charge pipeline is one feature of the present invention.

FIG. 11 illustrates one stage of a differential charge-domain pipeline ADC stage which implements the RSD algorithm. It is similar to the circuit of FIG. 10, except that the comparator, latch, logic block, and conditionally-switched capacitors are duplicated. Moreover, the two comparators are provided with shifted thresholds, such that each one switches at a specific charge imbalance between the “A” and “B” storage nodes, rather than switching at the point of balance as in FIG. 10. The comparators typically, although not necessarily, have thresholds symmetrical about the balance point, as indicated in FIG. 11. The two latched comparator decisions are output from the stage as digital signals b and b′.

Assuming that the stage of FIG. 11 is placed in a pipeline where its input charge range is the same as that of the binary stage of FIG. 10, then each of the conditionally-switched capacitors in FIG. 11 is half the size of the corresponding capacitors in FIG. 10. Thus, if both comparators in FIG. 11 are driven to the same decision, indicating a large charge difference between the “A” and “B” storage nodes, then both output bits b and b′ have the same value, and both conditionally-switched capacitors on the same branch of the differential charge pair are switched. In this case the stage charge transfer function is given by Equation 5, just as with the circuit of FIG. 10. If the input charge is nearly balanced, however, then b and b′ are complementary, and a charge of ½Q_(STAGE) is added to each outgoing charge packet. In this case the outgoing (differential) signal charge is not changed (Q_(OUT)=Q_(IN)).

One result of these operations is that the stage's output charge still obeys Equation 7. Another is that the extra bit resolved per stage provides the desired redundancy, so that later bit-decisions can be used to correct earlier, less exact ones. Thus the improved charge resolution in later stages, provided by the tapered pipeline, can be used to provide overall improved ADC resolution. The charge scaling from stage to stage in this example is still a factor of 2, just as with the binary pipeline ADC described above.

FIGS. 8 and 9 illustrate two examplary applications of the principles of this invention to A/D conversion. Similar methods, based on the same principles, will be apparent to those familiar with the current ADC art. Examples include pipeline ADCs resolving two or more bits per stage, by using multiple comparators and conditionally-switched capacitor pairs.

The tapered-pipeline principle has been described principally with reference to a differential charge pipeline. In some applications, such as those where the input signal to be converted is a single-ended charge (as in an imager), a single-ended ADC pipeline configuration is preferable. The tapered-pipeline principle can be applied equally well to such applications.

While this invention has been particularly shown and described with references to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims. 

1. A charge domain pipeline using bucket brigade charge transfer comprising: a first charge transfer circuit; a second charge transfer circuit; a node coupled to the first charge transfer circuit and the second charge transfer circuit; a capacitor coupled to the node and to a clocked voltage; a switched voltage coupled to the node; and at least one of the first or second charge transfer circuits being a boosted charge transfer circuit.
 2. The charge domain pipeline of claim 1 additionally comprising: control circuitry configured to provide independent control of charge storage and charge transfer timing between the first charge transfer circuit and the second charge transfer circuit.
 3. The charge domain pipeline of claim 2 wherein the control circuitry provides control of charge-transfer direction in the pipeline.
 4. The charge domain pipeline of claim 1 comprising: a second capacitor coupled to the node and to a conditional voltage, the second capacitor configured to provide conditional charge to the node.
 5. The charge domain pipeline of claim 4 wherein the second capacitor provides conditional charge to the node based on a comparison of the voltage of the node with a reference voltage.
 6. The charge domain pipeline of claim 4 further comprising a plurality of capacitors coupled to the node and to conditional voltages, each of the plurality of capacitors configured to provide conditional charge to the node.
 7. The charge domain pipeline of claim 1 arranged to provide a differential charge domain pipeline and further comprising: a third charge transfer circuit, a fourth charge transfer circuit, a second node coupled to the third charge transfer circuit and the fourth charge transfer circuit; a second capacitor coupled to the node and to a second clocked voltage; and a third and fourth capacitor coupled respectively to the first node and second node and configured to provide conditional charge to either the first charge transfer circuit or the third charge transfer circuit.
 8. The differential charge domain pipeline of claim 7 wherein at least one of the third charge transfer circuit or the fourth charge transfer circuit is a boosted charge transfer circuit.
 9. The differential charge domain pipeline of claim 7 wherein the third capacitor provides conditional charge based on a comparison of the voltages of the first node and the second node.
 10. The differential charge domain pipeline of claim 7 further comprising a plurality of conditional charge capacitors coupled to the first and second node and configured to provide conditional charge to either the first charge transfer circuit or the third charge transfer circuit.
 11. The differential charge domain pipeline of claim 10 wherein the plurality of capacitors provide conditional charge based on comparisons of the voltages of the first node and the second node at different thresholds.
 12. A pipelined charge domain analog-to-digital converter using bucket brigade charge transfer comprising: a first charge transfer circuit; a second charge transfer circuit; a node coupled to the first charge transfer circuit and the second charge transfer circuit; a capacitor coupled to the node and to a clocked voltage; a switched voltage coupled to the node; and wherein at least one of the first or second charge transfer circuit is a boosted charge transfer circuit.
 13. The pipelined charge domain analog-to-digital converter of claim 12 additionally comprising: control circuitry configured to provide independent control of charge storage and charge transfer timing between the first charge transfer circuit and the second charge transfer circuit.
 14. The charge domain pipeline of claim 12 arranged to provide a differential charge domain pipeline and further comprising: a third charge transfer circuit; a fourth charge transfer circuit; a second node coupled to the third charge transfer circuit and the fourth charge transfer circuit; a second capacitor coupled to the node and to a second clocked voltage; and a third and fourth capacitor coupled to the first node and second node respectively and configured to provide conditional charge to either the first charge transfer circuit or the third charge transfer circuit.
 15. A pipelined charge domain analog-to-digital converter using bucket brigade charge transfer comprising: a first charge transfer circuit; a second charge transfer circuit; a node coupled to the first charge transfer circuit and the second charge transfer circuit; a first clocked capacitor coupled to the node and to a clocked voltage; a plurality of conditional charge capacitors coupled to the node and to conditional voltages, each of the plurality of conditional charge capacitors configured to provide conditional charge to the node.
 16. The pipelined charge domain analog-to-digital converter of claim 15 additionally comprising: a third charge transfer circuit, a fourth charge transfer circuit, a second node coupled to the third charge transfer circuit and the fourth charge transfer circuit; a second clocked capacitor coupled to the node and to a clocked voltage; a second plurality of conditional charge capacitors coupled to the first node and second node and configured to provide conditional charge to either the first charge transfer circuit or the third charge transfer circuit based on comparisons of the voltages of the first node and the second node at different thresholds.
 17. The pipelined charge domain analog-to-digital converter of claim 15 wherein the pipeline is enabled to implement an RSD analog-to-digital conversion algorithm.
 18. The pipelined charge domain analog-to-digital converter of claim 15 wherein the pipeline is enabled to implement binary stage scaling.
 19. A pipelined charge domain analog-to-digital converter using bucket brigade charge transfer comprising: a plurality of charge transfer circuits coupled in a cascading arrangement through a plurality of nodes, each node further coupled to a respective capacitor, with later nodes in the pipeline coupled to capacitors having a smaller capacitance than capacitors coupled to earlier nodes.
 20. The charge domain pipeline of claim 19 arranged to provide a differential charge domain pipeline and further comprising: a third charge transfer circuit; a fourth charge transfer circuit; a second node coupled to the third charge transfer circuit and the fourth charge transfer circuit; a second capacitor coupled to the node and to a second clocked voltage; and a third and fourth capacitor coupled to the first node and second node respectively and configured to provide conditional charge to either the first charge transfer circuit or the third charge transfer circuit.
 21. A pipelined charge domain analog-to-digital converter using bucket brigade charge transfer comprising: a plurality of charge transfer circuits coupled in a cascading arrangement through a plurality of nodes, each node further coupled to a respective capacitor, where the maximum output charge provided by each node is less that earlier nodes; and control circuitry configured to provide independent control of charge storage and charge transfer timing between the plurality of charge transfer circuits. 